product brief november 1999 orca ? or3lxxxb series field-programmable gate arrays features n high-performance, cost-effective, 0.25 m 5-level metal technology. n 2.5 v internal supply voltage and 3.3 v i/o supply voltage for speed and compatibility. n up to 340,000 usable gates in 0.25 m. n up to 612 user i/os in 0.25 m. (or3lxxxb i/os are 5 v tolerant to allow interconnection to both 3.3 v and 5 v devices, selectable on a per-pin basis, when using 3.3 v i/o supply.) n twin-quad programmable function unit (pfu) architecture with eight 16-bit look-up tables (luts) per pfu, organized in two nibbles for use in nibble- or byte-wide functions. allows for mixed arithmetic and logic functions in a single pfu. n nine user registers per pfu, one following each lut, plus one extra. all have programmable clock enable and local set/reset, plus a global set/reset (gsrn) that can be disabled per pfu. n flexible input structure (fins) of the pfus pro- vides a routability enhancement for luts with shared inputs and the logic flexibility of luts with independent inputs. n fast-carry logic and routing to adjacent pfus for nibble-wide, byte-wide, or longer arithmetic func- tions, with the option to register the pfu carry-out. n softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu. n supplemental logic and interconnect cell (slic) provides 3-statable buffers, up to 10-bit decoder, and pa l *-like and-or-invert (aoi) in each pro- grammable logic cell (plc). n abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementa- tions and less routing delay. n individually programmable drive capability: 12 ma sink/6 ma source or 6 ma sink/3 ma source. n built-in boundary scan ( ieee ? 1149.1 jtag) and ts_all testability function to 3-state all i/o pins. n enhanced system clock routing for low-skew, high- speed clocks originating on-chip or at any i/o. n up to four expressclk inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. n stopclk feature to glitchlessly stop/start the expressclks independently by user command. programmable i/o (pio) has: fast-capture input latch and input flip-flop (ff)/ latch for reduced input setup time and zero hold time. capability to (de)multiplex i/o signals. fast access to slic for decodes and pa l -like functions. output ff and two-signal function generator to reduce clk to output propagation delay. n fast open-drain drive capability. n new programmable i/o 3-state ff allows 3-state buffer control signals to be set up a clock cycle early for improved clock to output delays * pa l is a trademark of advanced micro devices, inc. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc. ? the usable gate counts range from a logic-only gate count to a gate count assuming 30% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates/pfu), including 12 gates per lut/ff pair (eight per pfu) , and 12 gates per slic/ff pair (one per pfu). each of the four pios per pic is counted as 16 gates (three ffs, fast-capture latch, o utput logic, clk, and i/o buffers). pfus used as ram are counted at four gates per bit, with each pfu capable of implementing a 32 x 4 ram (or 512 gates) per pfu. table 1. lucent technologies orca or3lxxxb series fpgas device system gates ? luts registers max user ram user i/os array size process technology OR3L165B 120k244k 8192 10752 131k 516 32 x 32 0.25 m/5 lm or3l225b 166k340k 11552 14820 185k 612 38 x 38 0.25 m/5 lm
2 2 lucent technologies inc. product brief november 1999 orca or3lxxxb series fpgas system-level features system-level features reduce glue logic requirements and make a system on a chip possible. these features in the orca or3lxxxb include: n full pci local bus compliance for all devices in 3.3 v and 5 v pci systems. pin-selectable i/o clamping diodes provide 3.3 v and 5 v compliance and 5 v tolerance. n dual-use microprocessor interface (mpi) can be used for configuration, readback, device control, and device status, as well as for a general-purpose inter- face to the fpga. glueless interface to i960 * and powerpc ? processors with user-configurable address space provided. n parallel readback of configuration data capability with the built-in microprocessor interface. n programmable clock manager (pcm) adjusts clock phase and duty cycle for input clock rates from 5 mhz to 120 mhz. the pcm may be combined with fpga logic to create complex functions, such as dig- ital phase-locked loops (dpll), frequency counters, and frequency synthesizers or clock doublers. two pcms are provided per device. n true internal 3-state, bidirectional buses with simple control provided by the slic. n 32 x 4 ram per pfu, configurable as single- or dual- port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. n full utopia level iii i/o compliance (5.0 ns clk -> out, 2.0 ns setup with 0 ns hold). * i960 is a re g istered trademark of intel corporation. ? powerpc is a re g istered trademark of international business machines, inc. table 2 . orca series 3l system performance 1. implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. implemented using two 32 x 12 roms and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 pfus contain only pipelining registers). 4. implemented using 32 x 4 ram mode with read data on 3-state buffer to bidirectional read/write bus. 5. implemented using 32 x 4 dual-port ram mode. 6. implemented in one partially occupied slic with decoded output set up to ce in same plc. 7. implemented in five partially occupied slics. parameter # pfus -7 -8 unit 16-bit loadable up/down counter 2 151 176 mhz 16-bit accumulator 2 151 176 mhz 8 x 8 parallel multiplier: multiplier mode, unpipelined 1 rom mode, unpipelined 2 multiplier mode, pipelined 3 11.5 8 15 38 93 129 46 116 152 mhz mhz mhz 32 x 16 ram (synchronous): single-port, 3-state bus 4 dual-port 5 4 4 173 231 209 277 mhz mhz 128 x 8 ram (synchronous): single-port, 3-state bus 4 dual-port 5 8 8 151 151 181 181 mhz mhz 8-bit address decode (internal): using softwired luts using slics 6 0.25 0 2.30 1.29 2.00 1.12 ns ns 32-bit address decode (internal): using softwired luts using slics 7 2 0 7.97 3.75 6.84 3.16 ns ns 36-bit parity check (internal) 2 7.97 6.84 ns
lucent technologies inc. 3 product brief november 1999 orca or3lxxxb series fpgas ordering information OR3L165B, -7 speed grade, 240-pin power quad shrink flat package (sqfp2), commercial temperature table 3. voltage options table 4. temperature options table 5. package options table 6. orca or3lxxxb series package matrix note: c = commercial, i = industrial. device voltage or3lxxxb 2.5 v internal/3.3 v i/o symbol description temperature (blank) commercial 0 c to 70 c i industrial C40 c to +85 c symbol description ba plastic ball grid array (pbga) bc enhanced ball grid array (ebga) bm plastic ball grid array, multilayer (pbgam1) ps power quad shrink flat package (sqfp2) devices 208-pin eiaj/sq 240-pin eiaj/sq 352-pin pbga 432-pin pbga 680-pin pbgam OR3L165B ci ci ci ci ci or3l225b ci ci speed grade package type -7 ps number of pins temperature range 240 OR3L165B device type
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. copyright ? 1999 lucent technologies inc. all rights reserved printed in u.s.a. november 1999 pn00-012fpga (replaces pn99-053fpga) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)
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